1. The Field of the Invention
The present invention relates to the field of Application Specific Integrated Circuit (ASIC) design and tooling. In particular, the present invention relates to systems and methods for reducing the number of base wafer designs and reducing tooling costs associated with design and fabrication of structured and platform ASIC devices.
2. Background and Related Art
Various approaches are used to build custom logic Integrated Circuit (“IC”) devices. Different components, such as, for example, prefabricated Programmable Logic Devices (“PLDs”) (sometimes referred to as Field Programmable Gate Arrays (“FPGAs”)), gate arrays, standard cells (sometimes referred to as cell-based ICs), and hand-crafted custom logic, can be used to implement a custom logic IC device. Each of the different components is associated with a number of design parameters, such as, for example, development cost, unit cost, design cycle time, manufacturing cycle time, flexibility, risk, complexity, performance, and power consumption. Accordingly, selection of a particular component for use in a custom logic IC can be made based on the design parameters of the component.
FPGA devices are essentially high-volume standard products and are cost effective for low-volume or low-complexity devices. On the other hand, cell-based and hand-crafted custom ICs may be more appropriate for high-volume high-complexity devices. In between, gate-array devices have typically been used to implement medium-complexity, medium-volume devices.
However, gate arrays often lack the flexibility to support more complex functionality such as, for example, large amounts of memory, timing generator functions and other specialized functions (e.g., processors and I/O physical interfaces). Thus, cell-based and hand-crafted custom ICs are used to implement this more complex functionality. Unfortunately, with advances in process technology, the resulting development cost of cell-based and hand-crafted custom IC's is rising exponentially, due at least in part to the cost of photolithographic reticle tooling. This increased development cost essentially limits the use of cell-based and hand-crafted custom IC's to very high-volume cost-sensitive applications. That is, it may be difficult to implement high-complexity low-volume applications in a cost efficient manner.
More recently, a new class of devices, often referred to as Structured ASICs, has emerged to fill the gap between the FPGA and cell-based approaches. Structured ASICs utilize pre-fabricated base wafers which include resources for logic, memory, timing generators and may include other specialized functional blocks, commonly referred to as Intellectual Property (IP). The base wafers are then personalized with a reduced number of customized metal and/or via interconnection levels to produce the desired custom logic device. Structured ASICs share similarity with gate arrays in that both use a base wafer approach. Like gate arrays, each Structured ASIC family requires a set of bases (e.g., from 6 to 12), covering a range of silicon die sizes to address the needs of different size devices and corresponding packages.
However, structured ASICs differ from gate arrays by including more embedded functions and by pre-designing or fixing more interconnection layers. By minimizing the number of customized interconnection levels required, the tooling development costs can be reduced significantly. Other recent tooling mechanisms use more advanced process technology (i.e., more expensive tooling) for base wafers and less advanced process technology (i.e., less expensive tooling) for the customized levels. These more recent mechanisms distribute the development cost of the base wafer across multiple custom logic devices to reduce overall development cost. Along with relatively lower development cost for a small number of less expensive customized interconnect level tooling, the total tooling cost for a device may be substantially reduced.
One challenge in selecting the architecture of structured ASIC devices is deciding what type of and in what quantity pre-designed functional blocks should be embedded in the base. If the appropriate IP functions are not included, the corresponding device will not be usable for certain applications. If too many embedded IP functions are unused in a particular application, significant silicon area will be unused, potentially making the cost of the device too high.
One solution is to build a special type of structured ASIC called a platform ASIC that addresses the needs of a particular set of applications. For example, a communications platform ASIC might include I/O processing cores and I/O physical interfaces, whereas a signal processing platform ASIC might include Digital Signal Processing (DSP) processing components and A/D and D/A converters. However, developing multiple platforms each requiring a number of bases (e.g., 6 to 12) requires a significant financial investment.
Further, there are other tooling costs in addition to the photolithographic reticles discussed above. These costs include reticles for flip-chip style pad ReDistribution Layers (“RDLs”), wafer probe cards, and customized IC package development. Each base in a Structured (or Platform) ASIC family will require these additional types of tooling, and thus, will incur some additional corresponding cost, which can usually be distributed across multiple custom logic devices.
Prior art contains various approaches to reducing the number of base wafers required to implement a gate array family. One approach uses a borderless gate array to print a sea of transistors across the surface of the die. The actual die border is defined by scribe lines in the programmable levels. In this manner a one-size-fits-all base is created from which different size die can be created.
However, the borderless approach faces several problems. One problem is finding an effective way to achieve isolation from the scribe line region. Scribe lines defined in the programmable levels may provide good definition of the cutting region but since scribe lines typically do not extend into base layers, good isolation is difficult to achieve.
A second problem arises due to the intrinsic differences between transistors designed for use in core logic functions and those intended for use in I/O functions. Typically the I/O transistors are much larger, operate with different voltages and require special ESD protection structures. With the borderless approach it is desirable to be able to use any part of the base for core logic functions and any part for I/O functions. Various approaches have been used to achieve dual-use transistors, but the disparity in core and I/O transistor requirements continues to widen, making it evermore difficult to create efficient dual-use structures.
Most borderless approaches do not handle alignment marks and other photolithograhic and processing artifacts very efficiently, often resulting in significant wasted silicon real estate. Accordingly, it may be difficult to align repeating patterns on the base with repeating patterns on programmable levels. Many existing mechanisms avoid this alignment issue by intentionally wasting space. As such they are typically directed to prototyping and are typically not useful for volume production.
Prior art also includes the concept of a base wafer with borders in one-dimension. These borders effectively create strips of core cell logic functions and I/O functions. The strip dimensions are fixed in one direction, but as wide as the wafer in the other direction, permitting a range of rectangular sized die to be created by defining scribe lines in the programmable levels.
To some extent, the one-dimensional bordered arrays solve the problem of sharing core logic and I/O functions. However, one-dimensional bordered arrays require that I/O functions are restricted to running along the two side borders. Thus, problems with isolation in the scribe line regions in the unbordered direction and problems with repeating patterns of alignment and other manufacturing artifacts still exist.
Additionally, prior art includes base wafers with borders in two-dimensions. The resulting rectangular regions may be clustered or stitched together to form a larger die. However, these two-dimensional bordered arrays have been limited to the traditional sea-of-transistor architecture. They use traditional I/O ring architectures and route I/O from the interior portions of the I/O rings to wire-bond pads around the periphery of the final die. Some two-dimensional bordered arrays include circuitry in the scribe line regions specifically for bridging signals from one region to another.
The two-dimensional bordered arrays solve some of the scribe line, core logic and I/O function problems. However, problems related to isolating circuitry in the scribe line regions and dealing with the multitude of alignment, manufacturing and testing artifacts placed on a wafer surrounding the individual die still exist. These problems are particularly acute when the base die reticle fields have a different repeat sequence than the programmable level reticle fields. Accordingly, what would be advantageous are systems and methods for reducing the number of bases and reducing base tooling expenses associated with structured and platform ASICs while optimizing die size for individual applications.